ABSTRACTS AND PRESENTATION DESCRIPTIONS SESSION 1: EDA TOOL PRESENTATIONS Catapult Synthesis: a Proven Approach for the Creation of Complex Hardware Designs Bollaert, Mentor Graphics FR How to Make Algorithmic Synthesis as Ubiquitous as Logic Synthesis

S AND PRESENTATION DESCRIPTIONS SESSION 1: EDA TOOL PRESENTATIONS Catapult Synthesis: a Proven Approach for the Creation of Complex Hardware Designs Bollaert, Mentor Graphics FR How to Make Algorithmic Synthesis as Ubiquitous as Logic Synthesis V Kathail, Synfora, US Cynthesizer: the Forte SystemC synthesis tool M Meredith, Forte Design Systems, US New Opportunities for High-Level Synthesis J Cong, UCLA/AutoESL, US New Opportunities for High-Level Synthesis Jason Cong [email protected] Professor and Chair UCLA Computer Science Department http://cadlab.cs.ucla.edu/~cong Chief Technology Advisor AutoESL Design Technologies, Inc. www.autoesl.com The rapid increase of complexity in System-on-a-Chip design urges the design community to raise the level of abstraction beyond RTL. Automated behavior level and system-level synthesis are naturally identified as next steps to replace RTL synthesis and will greatly boost the adoption of electronic system-level (ESL) design. High-level executable specifications, such as C, C++, or SystemC, are also preferred for system-level verification and hardware/software co-design. Power minimization also requires optimization at the highest level of abstraction, giving another demand for ESL. Finally, C/C++ based compilation flow are very much needed for FPGAbased accelerated computing, which has made great progress in the past decade. In this talk, we shall discuss these opportunities in detail, and also present a platform-based, constraint-driven ESL synthesis system, named AutoPilotTM offered by AutoESL Design Technologies, Inc. AutoPilot is based on the xPilot system originally developed at UCLA. It automatically generates efficient RTL code from C, C++ or SystemC descriptions for a given system platform and simultaneously optimize logic, interconnects, performance, and power. Experimental results demonstrate very promising results for a wide range of applications, including hardware synthesis, system-level design exploration, and reconfigurable accelerated computing. SESSION 2: RESEARCH DIRECTIONS HLS and Cost of Design R Gupta, UCSD , US Multi-Mode Architecture Design with High-Level Synthesis P Coussy, University of South Brittany, FR Ant Colony Optimization for High Level Synthesis R Kastner, UCSB, US User Guided High level synthesis F Pétrot, TIMA Laboratory, FR Speaker : P Coussy Title : Multi-Mode Architecture Design with High-Level Synthesis Abstract This presentation addresses the design of multi-mode architectures for digital signal processing applications. We introduce a dedicated design flow and its associated high-level synthesis tool. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized in area is generated. In order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. We will show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art. First results on power consumption will also be provided. SESSION 3: POSTER S/ DEMONSTRATION S/ INTERACTIVE PRESENTATIONS SESSION 4 : THE FUTURE OF HIGH-LEVEL SYNTHESIS The Limits of Current HLS Offer : What is Needed for a Wider Adoption P Urard, STMicroelectronics, FR "All-in-C" SoC Synthesis and Verification with CyberWorkBench K Wakabayashi, NEC, JP Enabling DSP System Designs with High Level Design Methodologies & Tools J Heighton, Xilinx, IR Industrial Usage of High-Level Synthesis W Ecker, Infineon , DE Synthesis Semantics for SystemC A Takach, Chair of the OSCI Synthesis Working Group, US Speaker : P Coussy Title : Multi-Mode Architecture Design with High-Level Synthesis Abstract This presentation addresses the design of multi-mode architectures for digital signal processing applications. We introduce a dedicated design flow and its associated high-level synthesis tool. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized in area is generated. In order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. We will show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art. First results on power consumption will also be provided.